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june 2016 docid026184 rev 2 1 / 14 this is information on a product in full production. www.st.com STF7N105K5 n - channel 1050 v, 1.4 typ., 4 a mdmesh? k5 power mosfet in to - 220fp package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d p tot STF7N105K5 1050 v 2.0 4 a 25 w ? industrys lowest r ds(on) x area ? industrys best fom (figure of merit) ? ultra - low gate charge ? 100% avalanche tested ? zener - protected applications ? switching applications description this very high voltage n - channel power mosfet is designed using mdmesh? k5 technology based on an innovative proprietary vertical structure. the result is a dramatic r eduction in on - resistance and ultra - low gate charge for applications requiring superior power density and high efficiency. table 1: device summary order code marking packag e packaging STF7N105K5 7n105k5 to - 220fp tube am15572v1_no_tab d(2) g(1) s(3) t o-220f p
contents STF7N105K5 2 / 14 docid026184 rev 2 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 2.1 electrical characteri stics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 9 4 package information ................................ ................................ ..... 10 4.1 to - 220fp package information ................................ ...................... 11 5 revision history ................................ ................................ ............ 13
STF7N105K5 electrical ratings docid026184 rev 2 3 / 14 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 30 v i d drain current (continuous) at t c = 25 c 4 (1) a i d drain current (continuous) at t c = 100 c 3 (1) a i dm (2) drain current (pulsed) 16 a p tot total dissipation at t c = 25 c 25 w i ar max. current during repetitive or single pulse avalanche 1.5 a e as single pulse avalanche energy (starting t j = 25 c, i d =i ar , v dd = 50 v) 132 mj v iso insulation withstand voltage (rms) from all three leads to ex ternal heat sink (t = 1 s; t c = 25 c) 2 500 v dv/dt (3) peak diode recovery voltage slope 4.5 v/ns dv/dt (4) mosfet dv/dt ruggedness 50 v/ns t j operating junction temperature range - 55 to 150 c t stg storage temperature range notes: (1) limited by package. (2) pulse width limited by safe operating area. (3) i sd 4 a, di/dt 100 a/s, v ds(peak) v (br)dss ; v sd 840 v (4) v ds 840 v table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case max 5 c/w r thj - amb thermal resistance junction - amb max 62.5 c/w
electrical characteristics STF7N105K5 4 / 1 4 docid026184 rev 2 2 electrical characteristics (t case = 25 c unless otherwise specified). table 4: on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 1050 v i dss zero gate voltage drain current v gs = 0 v, v ds = 1050 v 1 a v gs = 0 v , v ds = 1050 v, t c =125 c (1) 50 a i gss gate body leakage current v ds = 0, v gs = 20 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 3 4 5 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 2 a 1.4 2 notes: (1) defined by design, not subject to production test. table 5: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds =100 v, f=1 mhz, v gs =0 v - 380 - pf c oss output capacitance - 40 - pf c rss reverse transfer capacitance - 0.65 - pf c o(tr) (1) equivalent capacitance time related v gs = 0 v, v ds = 0 to 840 v - 47 - pf c o(er) (2) equivalent capacitance energy related - 17 - pf r g intrinsic gate resistance f = 1mhz open drain - 7 - q g total gate charge v dd = 840 v, i d = 4 a v gs =10 v figure 16: "test circuit for gate charge behavior" - 11 - nc q gs gate - source charge - 2.8 - nc q gd gate - drain charge - 5.6 - nc notes: (1) time related is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss (2) energy related is defined as a constant equivalent capacitance giving the same stored energy as c oss when v ds increases from 0 to 80% v dss
STF7N105K5 electrical characteristics docid026184 rev 2 5 / 14 table 6: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 525 v, i d = 2 a, r g =4.7 , v gs =10 v (see figure 15: "test circuit for resistive load switching times" and figure 20: "switching time waveform" ) - 17.5 - ns t r rise time - 7 - ns t d(off) turn - off delay time - 43 - ns t f fall time - 25 - ns table 7: source drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 4 a i sdm source - drain current (pulsed) 16 a v sd (1) forward on voltage i sd = 4 a, v gs =0 - 1.6 v t rr reverse recovery time i sd = 4 a, v dd = 60 v di/dt = 100 a/s, figure 17: "test circuit for inductive load switching and diode recovery times" - 370 ns q rr reverse recovery charge - 3 c i rrm reverse recovery current - 16.5 a t rr reverse recovery time i sd = 4 a,v dd = 60 v di/dt=100 a/s, tj=150 c figure 17: "test circuit for inductive load switching and diode recovery times" - 600 ns q rr reverse recovery charge - 4.4 c i rrm reverse recovery current - 14.5 a notes: (1) pulsed: pulse duration = 300s, duty cycle 1.5% table 8: gate - source zener diode symbol parameter test conditions min typ. max. unit v (br)gso gate - source breakdown voltage i gs = 1ma, i d =0 30 - - v the built - in back - to - back zener diodes have been specifically designed to enhance the esd capability of the device. the zener voltage is appropriate for efficient and cost - effective intervention to protect the device integrity. these integrated zener diodes thus elimi nate th e need for external components.
electrical characteristics STF7N105K5 6 / 14 docid026184 rev 2 2.1 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance
STF7N105K5 electrical characteristics docid026184 rev 2 7 / 14 figure 8 : capacitance variations figure 9 : source - drain diode forward characteristics figure 10 : normalized gate threshold voltage vs temperature figure 11 : normalized on - resistance vs temperature figure 12 : normalized v(br)dss vs temperature figure 13 : maximum avalanche energy vs starting tj e as 0 40 t j (c) (mj) 20 100 60 80 0 20 40 60 80 120 140 100 120 i d =1.5 a v dd =50 v gipg210320141421s a
electrical characteristics STF7N105K5 8 / 1 4 docid026184 rev 2 figure 14 : output capacitance stored energy
STF7N105K5 test circuits docid026184 rev 2 9 / 14 3 test circuits figure 15 : test circuit for resistive load switching times figure 16 : test circuit for gate charge behavior figure 17 : test circuit for inductive load switching and diode recovery times figure 18 : unclamped inductive load test circuit figure 19 : unclamped inductive waveform figure 20 : switching time waveform
package information STF7N105K5 10 / 14 docid026184 rev 2 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? speci fications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
STF7N105K5 package information docid026184 rev 2 11 / 14 4.1 to - 220fp package information figure 21 : t o - 220fp package outline
package information STF7N105K5 12 / 14 docid026184 rev 2 table 9: to - 220fp package mechanical data dim. mm min. typ. max. a 4.4 4.6 b 2.5 2.7 d 2.5 2.75 e 0.45 0.7 f 0.75 1 f1 1.15 1.70 f2 1.15 1.70 g 4.95 5.2 g1 2.4 2.7 h 10 10.4 l2 16 l3 28.6 30.6 l4 9.8 10.6 l5 2.9 3.6 l6 15.9 16.4 l7 9 9.3 dia 3 3.2
STF7N105K5 revision history docid026184 rev 2 13 / 14 5 revision history table 10: document revision history date revision changes 07 - apr - 2014 1 first release. 07 - jun - 2016 2 updated figure 6: "gate charge vs gate - source voltage" and table 5: "dynamic" . minor text changes.
STF7N105K5 14 / 14 docid026184 rev 2 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers s hould obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, select ion, and use of st products and st assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved

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